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PALLV22V10 PALLV22V10Z
COM'L: -7/10/15
IND: -15 IND: -25
PALLV22V10 and PALLV22V10Z Families
Low-Voltage (Zero Power) 24-Pin EE CMOS Versatile PAL Device DISTINCTIVE CHARACTERISTICS
x Low-voltage operation, 3.3 V JEDEC compatible x x x x x x x x x
GENERAL DESCRIPTION
The PALLV22V10 is an advanced PAL(R) device built with low-voltage, high-speed, electricallyerasable CMOS technology. The PALLV22V10Z provides low voltage and zero standby power. At 30 A maximum standby current, the PALLV22V10Z allows battery powered operation for an extended period.
The product terms are connected to the fixed OR array with a varied distribution from 8 to 16 across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial, and active high or active low. The output configuration is determined by two bits controlling two multiplexers in each macrocell.
Publication# 18956 Amendment/0
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The PALLV22V10 device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs.
Rev: F Issue Date: September 2000
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-- VCC = + 3.0 V to 3.6 V Commercial and industrial operating temperature range 7.5-ns tPD Electrically-erasable technology provides reconfigurable logic and full testability 10 macrocells programmable as registered or combinatorial, and active high or active low to match application needs Varied product term distribution allows up to 16 product terms per output for complex functions Global asynchronous reset and synchronous preset for initialization Power-up reset for initialization and register preload for testability Extensive third-party software and programmer support 24-pin SKINNY DIP and 28-pin PLCC packages save space
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BLOCK DIAGRAM
CLK/I0 1 11 I1 - I11
PROGRAMMABLE AND ARRAY (44 x 132)
8 10 12 14 16 16 14 12 10 8
RESET
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OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
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OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL PRESET
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9 18956D-001
FUNCTIONAL DESCRIPTION
The PALLV22V10 is the low-voltage version of the PALCE22V10. It has all the architectural features of the PALCE22V10. The PALLV2210Z is the low-voltage, zero-power version of the PALCE22V10. It has all the architectural features of the PALCE22V10. In addition, the PALLV22V10Z has zero standby power and an unused product term disable feature. The PALLV22V10 allows the systems engineer to implement a design on-chip by programming EE cells to configure AND and OR gates within the device, according to the desired logic function. Complex interconnections between gates, which previously required time-consuming layout, are lifted from the PC board and placed on silicon, where they can be easily modified during prototyping or production. Product terms with all connections opened assume the logical HIGH state; product terms connected to both true and complement of any single input assume the logical LOW state. The PALLV22V10 has 12 inputs and 10 I/O macrocells. The macrocell (Figure 1) allows one of four potential output configurations; registered output or combinatorial I/O, active high or active low (see Figure 2). The configuration choice is made according to the user's design specification and corresponding programming of the configuration bits S0 - S1. Multiplexer controls are connected to ground (0) through a programmable bit, selecting the "0" path through the multiplexer. Erasing the bit disconnects the control line from GND and it floats to VCC (1), selecting the "1" path. The device is produced with a EE cell link at each input to the AND gate array, and connections may be selectively removed by applying appropriate voltages to the circuit. Utilizing an easilyimplemented programming algorithm, these products can be rapidly programmed to any customized pattern.
2 PALLV22V10 and PALLV22V10Z Families
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Variable Input/Output Pin Ratio The PALLV22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Unused input pins should be tied to VCC or GND. Registered Output Configuration Each macrocell of the PALLV22V10 includes a D-type flip-flop for data storage and synchronization. The flip-flop is loaded on the LOW-to-HIGH transition of the clock input. In the registered configuration (S1 = 0), the array feedback is from Q of the flip-flop. Combinatorial I/O Configuration Any macrocell can be configured as combinatorial by selecting the multiplexer path that bypasses the flip-flop (S1 = 1). In the combinatorial configuration, the feedback is from the pin.
AR DQ CLK Q SP
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1 1 0 0 0 1 0 1 I/On S1 S1 0 0 1 1 S0
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S0 0 1 0 1
Output Configuration Registered/Active Low Registered/Active High Combinatorial/Active Low Combinatorial/Active High
0 1
0 = Programmed EE bit 1 = Erased (charged) EE bit
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18956C-004
Figure 1. Output Logic Macrocell Diagram
PALLV22V10 and PALLV22V10Z Families
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AR D CLK SP a. Registered/active low Q Q
S0 = 0 S1 = 0
S0 = 0 S1 = 1
b. Combinatorial/active low
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AR D CLK SP Q Q
c. Registered/active high
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S0 = 1 S1 = 0
S0 = 1 S1 = 1
d. Combinatorial/active high
18956D-005
Figure 2. Macrocell Configuration Options
Programmable Three-State Outputs
Programmable Output Polarity
The polarity of each macrocell output can be active high or active low, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save "DeMorganizing" efforts. Selection is controlled by programmable bit S0 in the output macrocell, and affects both registered and combinatorial outputs. Selection is automatic, based on the design specification and pin definitions. If the pin definition and output equation have the same polarity, the output is programmed to be active high (S0 = 1). Preset/Reset For initialization, the PALLV22V10 has additional preset and reset product terms. These terms are connected to all registered outputs. When the synchronous preset (SP) product term is asserted high, the output registers will be loaded with a HIGH on the next LOW-to-HIGH clock transition. When the asynchronous reset (AR) product term is asserted high, the output registers will be immediately loaded with a LOW independent of the clock.
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Each output has a three-state output buffer with three-state control. A product term controls the buffer, allowing enable and disable to be a function of any product of device inputs or output feedback. The combinatorial output provides a bi-directional I/O pin, and may be configured as a dedicated input if the buffer is always disabled.
PALLV22V10 and PALLV22V10Z Families
Note that preset and reset control the flip-flop, not the output pin. The output level is determined by the output polarity selected. Benefits of Lower Operating Voltage The PALLV22V10 has an operating voltage range of 3.0 V to 3.6 V. Low voltage allows for lower operating power consumption, longer battery life, and/or smaller batteries for notebook applications. Because power is proportional to the square of the voltage, reduction of the supply voltage from 5.0 V to 3.3 V significantly reduces power consumption. This directly translates to longer battery life for portable applications. Lower power consumption can also be used to reduce the size and weight of the battery. Thus, 3.3 V designs facilitate a reduction in the form factor.
3.3-V (CMOS) and 5-V (CMOS and TTL) Compatible Inputs and I/O Input voltages can be at TTL levels. Additionally, the PALLV22V10 can be driven with true 5-V CMOS levels due to special input and I/O buffer circuitry. Power-Up Reset
All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALLV22V10 will depend on the programmed output polarity. The VCC rise must be monotonic, and the reset delay time is 1000ns maximum. Register Preload
Security Bit
After programming and verification, a PALLV22V10 design can be secured by programming the security EE bit. Once programmed, this bit defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. When the security bit is programmed, the array will read as if every bit is erased, and preload will be disabled. The bit can only be erased in conjunction with erasure of the entire pattern. Programming and Erasing The PALLV22V10 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its unprogrammed state. Erasure is automatically performed by the programming hardware. No special erase operation is required.
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The registers on the PALLV22V10 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery.
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PALLV22V10 and PALLV22V10Z Families
A lower operating voltage results in a reduction of I/O voltage swings. This reduces noise generation and provides a less hostile environment for board design. A lower operating voltage also reduces electromagnetic radiation noise and makes obtaining FCC approval easier.
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Quality and Testability The PALLV22V10 offers a very high level of built-in quality. The erasability of the CMOS PALLV22V10 allows direct testing of the device array to guarantee 100% programming and functional yields. Technology The high-speed PALLV22V10 is fabricated with Vantis' advanced electrically-erasable (EE) CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be 3.3-V and 5-V device compatible. This technology provides strong input-clamp diodes, output slew-rate control, and a grounded substrate for clean switching.
If a macrocell is used in registered mode, switching pin CLK/I0 will not affect standby mode status for that macrocell. If a macrocell is used in combinatorial mode, switching pin CLK/I0 will affect standby mode status for that macrocell. This feature reduces dynamic ICC proportionally to the number of registered macrocells used. If all macrocells are used as registers and only CLK/I0 is switching, the device will not be in standby mode, but dynamic ICC will typically be <2 mA. This is because only the CLK/I0 buffer will draw current. The use of combinatorial macrocells will add on average 5 mA per macrocell (at 25 MHz) under these same conditions. When any input switches, the internal circuitry is fully enabled, and power consumption returns to normal. This feature results in considerable power savings for operation at low to medium frequencies. Product-Term Disable
On a programmed PALLV22V10Z, any product terms that are not used are disabled. Power is cut off from these product terms so that they do not draw current. Product-term disabling results in considerable power savings. This saving is greater at the higher frequencies. Further hints on minimizing power consumption can be found in a separate document entitled, Minimizing Power Consumption with Zero-Power PLDs.
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PALLV22V10 and PALLV22V10Z Families
The PALLV22V10Z features a zero-standby power mode. When none of the inputs switch for an extended period (typically 30 ns), the PALLV22V10Z will go into standby mode, shutting down most of its internal circuitry. The current will go to almost zero (ICC <30 A). The outputs will maintain the states held before the device went into the standby mode.
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Zero-Standby Power Mode
LOGIC DIAGRAM
CLK/I 0 1 (2) 0 1 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43 AR
1 D 0 1 0 1
24 (28) VCC
AR SP
1 Q Q 0 0
23 I/O 9 (27)
9
0 1 10
1 D AR Q 1 0 0 0 1 0 1
22 I/O 8 (26)
20 SP
Q
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D AR Q Q
I1
2 (3) 21
0 1
1 1 0 0 0 1 0 1
21 I/O 7 (25)
33
SP 0 1
1 D AR Q Q 1 0 0 0 1 0 1
I2
3 (4)
34
20 I/O 6 (24)
SP 0 1
1 D AR 1 Q Q 0 0 0 1 0 1
48 I3 4 (5)
49
19 I/O 5 (23)
SP 0 1
1 D AR Q Q 1 0 0 0 1 0 1
65 I4 5 (6)
66
18 I/O 4 (21)
SP 0 1
1 D AR 1 Q Q 0 0 0 1 0 1
82 I5 6 (7)
83
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17 I/O 3 (20)
SP 0 1
1 D AR Q Q 1 0 0 0 1 0 1
97 I6 7 (9)
98
16 I/O 2 (19)
110
SP 0 1
I7
8 (10)
111
1 D AR Q 1 0 0 0 1 0 1
15 I/O 1 (18)
121
Q
SP 0 1
I8
9 (11)
122
1 D AR 1 Q Q 0 0 0 1 0 1
14 I/O 0 (17)
130 SP
I9
10 (12) 11 (13)
0 1 131 SP 13 (16) 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43 I11
I
10
GND
12 (14)
18956D-006
PALLV22V10 and PALLV22V10Z Families
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . . .-65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . .-55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . . . . -0.5 V to +5.25 V DC Output or I/O Pin Voltage . . . . . . -0.5 V to +5.25 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +75C) . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0C to +75C Supply Voltage (VCC) with Respect to Ground. . . . . . . . . . . . . . . +3.0 V to +3.6 V
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . -40C to +85C Supply Voltage (VCC) with Respect to Ground. . . . . . . . . . . . . . . +3.0 V to +3.6 V
DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES
Parameter Symbol VOH Output HIGH Voltage Parameter Description Test Conditions Min 2.4 VCC -0.2 0.5 0.2 2.0 5.25 0.8 10 -100 10 -100 -5 -10/15 Commercial ICC (Static) Supply Current Outputs f = 0 MHz, Open (IOUT = 0 mA) -7 -15 Industrial -75 60 75 75 Max Unit V V V V V V A A A A mA mA mA mA IOH = -2 mA
VOL VIH VIL IIH IIL IOZH IOZL ISC
Output LOW Voltage Input HIGH Voltage Input LOW Voltage
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Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current
Notes: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
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VIN = VIH or VIL VCC = Min VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for all Inputs (Notes 1, 2) Guaranteed Input Logical LOW Voltage for all Inputs (Notes 1, 2) VIN = VCC, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = VCC, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3)
PALLV22V10 - 7/10/15 (Com'l), -15 (Ind'l)
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Operating ranges define those limits between which the functionality of the device is guaranteed.
IOH = -100 A IOL = 16 mA IOL = 100 A
CAPACITANCE 1
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance VIN = 2.0 V VOUT = 2.0 V Test Condition VCC = 3.3 V TA = 25C f = 1 MHz Typ 5 8 pF Unit
Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
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-7 Parameter Description Min 4.5 0
SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES 1
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Max 7.5
Parameter Symbol tPD tS1 tS2 tH tCO tAR tARW tARR tSPR tWL tWH fMAX tEA tER
-10 Min 5.5 7 0 6.5 13 8 8 8 4 4 83.3 110 125 11 11 10 10 10 6 6 50 58.8 83.3 Max 10 10 10 0 Min
-15 Max 15 Unit ns ns ns ns 10 20 ns ns ns ns ns ns ns MHz MHz MHz 15 15 ns ns
Input or Feedback to Combinatorial Output Setup Time from SP to Clock Hold Time Clock to Output
Setup Time from Input, Feedback or SP to Clock
5.5
5.5 11
Asynchronous Reset to Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time Clock Width LOW
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6 6
3.5
HIGH
3.5
External Feedback
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Maximum Frequency (Note 2)
Internal Feedback (fCNT)
1/(tS + tCO) 1/(tS + tCF) (Note 3)
100
133
No Feedback
1/(tWH + tWL)
143
Input to Output Enable Using Product Term Control Input to Output Disable Using Product Term Control
9 10
Notes: 1. See "Switching Test Circuit" for test conditions. 2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS.
PALLV22V10 - 7/10/15 (Com'l), -15 (Ind'l)
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . . .-65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . .-55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . . . . . -0.5 V to +5.5 V DC Output or I/O Pin Voltage . . . . . . . -0.5 V to +5.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = -40C to 85C). . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . -40C to +85C Supply Voltage (VCC) with Respect to Ground. . . . . . . . . . . . . . . +3.0 V to +3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Test Conditions Min 2.4 VCC -0.3 0.4 0.2 2.0 5.5 0.8 10 -10 10 -10 -5 f = 0 MHz f = 15 MHz -75 30 55 Max Unit V V V V V V A A A A mA A mA VIN = VIH or VIL VCC = Min VIN = VIH or VIL VCC = Min IOH = -2 mA IOH = -100 A IOL = 2 mA IOL = 100 A
Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW
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Input HIGH Leakage Current
Output Short-Circuit Current Supply Current
Notes: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is guaranteed under worst case test conditions. Refer to the ICC vs. Frequency graph in this datasheet for typical ICC characteristics.
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Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = VCC, VCC = Max VIN = 0 V, VCC = Max VOUT = VCC, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) Outputs Open (IOUT = 0 mA) VCC = Max (Note 4)
PALLV22V10Z-25
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CAPACITANCE 1
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance VIN = 2.0 V VOUT = 2.0 V Test Condition VCC = 3.3 V TA = 25C f = 1 MHz Typ 5 8 pF Unit
Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
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Parameter Description
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SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES 1
Parameter Symbol -25 Min 15 0 15 25 25 25 25 10 10 33.3 35.7 50 25 25 ns ns ns ns ns ns MHz MHz MHz ns ns Max 25 Unit ns ns ns
tPD
tS tH tCO tAR tARW tARR tSPR tWL tWH fMAX tEA tER
Input or Feedback to Combinatorial Output (Note 2) Setup Time from Input, Feedback or SP to Clock Hold Time Clock to Output
Asynchronous Reset to Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time Clock Width
LOW
HIGH
External Feedback
Maximum Frequency (Note 3)
Internal Feedback (fCNT)
1/(tS + tCO) 1/(tS + tCF) (Note 4)
No Feedback
1/(tWH + tWL)
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
Notes: 1. See "Switching Test Circuit" for test conditions. 2. This parameter is tested in Standby Mode. When the device is not in Standby Mode, the tPD may be slightly faster. 3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS.
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PALLV22V10Z-25
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SWITCHING WAVEFORMS
Input or Feedback Input or Feedback VT tPD Combinatorial Output VT
18956D-007
VT tS tH VT tCO
Clock
Registered Output
VT
18956D-008
a. Combinatorial output
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Input tER
b. Registered output
VT tEA VOH - 0.5V VOL + 0.5V VT
18956D-010
tWH Clock
VT
Output
tWL
c. Clock width
18956D-009
d. Input to output disable/enable
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Input Asserting Asynchronous Reset Registered Output
tARW
VT
Input Asserting Synchronous Preset
VT tS tH tSPR VT tCO
tAR
VT tARR
Clock
Clock
VT
18956D-011
Registered Output
VT
18956D-012
e. Asynchronous reset
f. Synchronous preset
Notes: 1. VT = 1.5 V for inputs signals and VCC/2 for outputs signals. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns to 5 ns typical.
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PALLV22V10 and PALLV22V10Z Families
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown
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Center Line is HighImpedance "Off" State VCC S1 R1 Output R2 S2
18956D-014
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18956D-013
SWITCHING TEST CIRCUIT
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Test Point CL
Specification tPD, tCO tEA tER Closed
S1 Closed Z H: Open Z L: Closed H Z: Closed L Z: Closed
S2 Z H: Closed Z L: Open H Z: Closed L Z: Open
CL 30 pF
R1
R2
Measured Output Value VCC/2
1.6K 5 pF
1.6K
VCC/2 H Z: VOH - 0.5 V L Z: VOL + 0.5 V
PALLV22V10 and PALLV22V10Z Families
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TYPICAL ICC CHARACTERISTICS
VCC = 3.3 V, TA = 25C
150
140 130
120
100 90
80 ICC (mA) 70
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10 15 20 25 30 35 40 45 Frequency (MHz)
110
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PALLV22V10-7 PALLV22V10-10/15 0
60
50 40 30 20
10
0 5 50
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ICC vs. Frequency
18956D-015
The selected "typical" pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half of the outputs were switching. By utilizing 50% of the device, a midpoint is defined for ICC. From this midpoint, a designer may scale the ICC graphs up or down to estimate the ICC requirements for a particular design.
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PALLV22V10 and PALLV22V10Z Families
ENDURANCE CHARACTERISTICS
The PALLV22V10 is manufactured using Vantis' advanced electrically-erasable (EE) CMOS process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed--a feature which allows 100% testing at the factory.
Symbol tDR N Parameter Min Pattern Data Retention Time Min Reprogramming Cycles Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions Value 10 20 100 Unit Years Years Cycles
ROBUSTNESS FEATURES
INPUT/OUTPUT EQUIVALENT SCHEMATICS
VCC VCC
> 50 K
ESD Protection and Clamping
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Programming Pins only Programming Voltage Detection
The PALLV22V10 has some unique features that make it extremely robust, especially when operating in high speed design environments. Input clamping circuitry limits negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A special noise filter makes the programming circuitry completely insensitive to any positive overshoot that has a pulse width of less than about 100 ns.
Positive Overshoot Filter
R
Programming Circuitry
Typical Input
VCC 5-V Protection
Provides ESD Protection and Clamping Preload Circuitry Feedback Input
18956D-017
Typical Output
PALLV22V10 and PALLV22V10Z Families
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POWER-UP RESET
The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are:
x x
The VCC rise must be monotonic. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met.
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Parameter Description
Parameter Symbol tPR tS tWL
R
Max 1000 See Switching Characteristics Unit ns Power-Up Reset Time Clock Width LOW Input or Feedback Setup Time
VCC
Power
2.7 V
tPR
Registered Active-Low Output
tS
Clock
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tWL
18956D-018
Figure 3. Power-Up Reset Waveform
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PALLV22V10 and PALLV22V10Z Families
TYPICAL THERMAL CHARACTERISTICS
PALLV22V10-10 Measured at 25C ambient. These parameters are not tested.
Parameter Symbol jc ja Typ Parameter Description Thermal impedance, junction to case Thermal impedance, junction to ambient 200 lfpm air jma Thermal impedance, junction to ambient with air flow 400 lfpm air 600 lfpm air 800 lfpm air SKINNY DIP 26 86 72 65 PLCC 20 69 57 52 47 45 Unit C/W C/W C/W C/W C/W C/W
Plastic jc Considerations The data listed for plastic jc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the jc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment.
U SE
G N AL EW D D EV ES IC IG ES NF SO
PALLV22V10 and PALLV22V10Z Families
R
60 55
17
CONNECTION DIAGRAMS
Top View
SKINNY DIP CLK/I0 PLCC VCC I/O9 I/O8 25 24
I2
I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 GND
2 3 4 5 6 7 8 9 10 11 12
23 22 21 20 19 18 17 16 15 14 13
I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I11 I3 I4 I5 NC I6 I7 I8 5 6 7 8 9 4 3 2 1 28 27 26 I/O7 I/O6 I/O5 GND/NC I/O4 I/O3 I/O2
I1
CLK/I0
1
24
VCC
R
12 13 14 15 16 17 18 GND NC I9 I/O0 I/O1 I10 I11
NC
23 22 21 20 19
G N AL EW D D EV ES IC IG ES NF SO
10 11
18956D-002
18956D-003
Note: Pin 1 is marked for orientation.
PIN DESIGNATIONS
CLK GND I I/O NC VCC = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage
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U SE
PALLV22V10 and PALLV22V10Z Families
ORDERING INFORMATION
Commercial and Industrial Products
Lattice/Vantis programmable logic products for commercial and industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of these elements:
PAL LV 22
V
10
-7 J
C
NUMBER OF ARRAY INPUTS OUTPUT TYPE V = Versatile NUMBER OF OUTPUTS Z = Zero Power (30 A ICC Standby)
G N AL EW D D EV ES IC IG ES NF SO
PALLV22V10 and PALLV22V10Z Families
TECHNOLOGY LV = Low-Voltage
R
SPEED -7 -10 -15 -25
FAMILY TYPE PAL = Programmable Array Logic
OPERATING CONDITIONS C = Commercial (0C to +75C) I = Industrial (-40C to +85C) PACKAGE TYPE P = 24-Pin 300 mil Plastic SKINNYDIP (PD3024) J = 28-Pin Plastic Leaded Chip
= = = =
7.5 ns tPD 10 ns tPD 15 ns tPD 25 ns tPD
Valid Combinations PALLV22V10-7 PALLV22V10-10 PALLV22V10-15 PALLV22V10Z-25 JC PC, JC PI, JI
U SE
PC, JC, JI
Valid Combinations The Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice/Vantis sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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